Faculty
Dr. Longyang Lin received the Ph.D. degree from the National University of Singapore, Singapore, in 2018. He is currently an Assistant Professor with the School of Microelectronics, Southern University of Science and Technology, Shenzhen, China. He has authored or co-authored more than 30 publications on journals and conference proceedings. He is a co-author of the book Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling (Springer, 2020). His research interests include ultra-low power VLSI circuits, self-powered sensor nodes, widely energy-scalable VLSI systems, compute-in-memory, and cryogenic circuits. He serves as Associate Editor of the IEEE Transactions on VLSI Systems, Technical Program Committee member and Session Chair of APCCAS 2022 and ICTA 2022. He was the recepient of the Takuo Sugano award for outstanding far-east paper of ISSCC 2022. He is an IEEE senior member.
Dr. Lin welcomes individuals passionate in research to join his research group. He has openings for Research Assistant Professor, Postdoctoral Fellows, Research Assistants, Graduate Students, as well as Internships. Interested individuals are invited to email a copy of his/her CV to his email address, with subject titled “Research position application <Position, Name>”.
Contact：linly@sustech.edu.cn
Education
2014-2018, Ph.D., National University of Singapore
2011-2013, M.Sc., Lund University
2007-2011, B.Sc., Ume? University & B.Eng., Shenzhen University
Employment
2021.05 – Present, Assistant Professor, Southern University of Science and Technology
2018.08 – 2021.04, Research Fellow, National University of Singapore
2017.05 – 2017.08, Visiting Scholar, Polytechnic of Turin
2013.12 – 2014.08, Research Engineer, National University of Singapore
Awards
ISSCC The Takuo Sugano Award for Outstanding Far-East Paper，2022
ISSCC Demonstration Session Certificate of Recognition，2022
ISSCC Demonstration Session Certificate of Recognition，2020
IEEE SSCS Singapore Chapter Award，2017 & 2018
ISSCC Student Travel Grant Award, 2017
Research Interest
Ultra-low power digital circuit design
Energy-efficient AI processor design
Compute-in-memory
On-chip sensor fusion
Cryogenic digital circuit design
Research Publications
1. H. Zhang, L. Lin, Q. Fang, M. Alioto, “Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design,” IEEE Journal of Solid-State Circuits (JSSC), early access.
2. J. Lan, Z. Li, Z. Chen, Q. Zhu, W. Wang, M. Zaheer, J. Lu, J. Liang, M. Shen, P. Chen, K. Chen, G. Zhang, Z. Wang, F. Zhou, L. Lin, Y. Li, “Improved Performance of HfxZnyO‐Based RRAM and its Switching Characteristics down to 4 K Temperature,” Adv. Electron. Mater. 2023, 9, 2201250.
3. Q. Duong, Q. Trinh, V. Nguyen, D. Dao, D. Luong, V. Hoang, L. Lin, J. Deepu, “A low-power charge-based integrate-and-fire circuit for binarized-spiking neural network,” Int J Circ Theor Appl. 2023; 51(7): 3404-3414.
4. L. Fassio, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, “Voltage reference with corner-aware replica selection/merging for 1.4-mV accuracy in harvested systems down to 3.9 pW, 0.2 V,” IEEE Access, vol.11, 3584-3596, 2023.
5. J. Basu, K. Ali, L. Lin, M. Alioto, “Picowatt-Power Analog Gain Stages in Super-Cutoff Region With Purely-Harvested Demonstration,” IEEE Solid-State Circuits Letters, vol. 5, 226-229, 2022.
6. W. Mao, K. Li, Q. Cheng, L. Dai, B. Li, X. Xie, H. Li, L. Lin, H. Yu, "A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 2, pp. 213-226, Feb. 2022, doi: 10.1109/TVLSI.2021.3128435.
7. H. Zhang*, L. Lin*, Q. Fang, U. Kalingage, M. Alioto, “Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023. (*equally credited authors)
8. Q. Fang, L. Lin*, H. Zhang, T. Wang, M. Alioto, “Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023. (*equally credited authors)
9. J. Li, Y. Dong, L. Lin, J. S. Y. Tan, F. J. Yi, J. Yoo, “Wireless Body-Area Network Transceiver ICs with Concurrent Body-Coupled Powering and Communication using Single Electrode,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023.
10. Y. Zheng, T. He, X. Liang, Z. Kong, L. Lin, J. Zhao, "Body-Channel Wireless Power Transfer Employing Transmitter-Side Received Power Monitoring and Maximum Point Tracking," 2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei, Taiwan, 2022, pp. 495-499.
11. H. Wu, J.H. Park, M. Zhang, L. Lin, R. Jiang, J.H. Choi, J. Yoo, “A 0.95 pJ/b 5.12 Gb/s/pin Charge-Recycling IOs with 47% Energy Reduction for Big Data Applications,” 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), Taipei, Taiwan, 2022.
12. H. Zhang*, L. Lin*, Q. Fang, M. Alioto, "On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design," 2022 Symposium on VLSI Circuits, Honolulu, HI, USA, 2022, pp. 140-141. (*equally credited authors)
13. K. A. Ahmed*, L. Lin*, P. S. Salamani, M. Alioto, "Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems," 2022 Symposium on VLSI Circuits, Honolulu, HI, USA, 2022, pp. 50-51. (*equally credited authors)
14. Q. Fang*, L. Lin*, Y. Z. Wong, H. Zhang, M. Alioto, “Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching”, 2022 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2022. (*equally credited authors)
15. L. Wu, J. Guo, R. Jiang, Y. Peng, H. Wu, J. Li, Y. Dong, M. Zhang, Z. Li, K. A. Ng, C.-W. Tsai, L. Zhang, L. Lin, L. Lin and J. Yoo, "BatDrone: A 9.83M-focal points/s, 7.76μs Latency Ultrasound Imaging Sensor SoC with On-Chip Per-Voxel RX Beam-Focusing for 7-m Range Drone Applications", 2022 IEEE International Solid-State Circuits Conference (ISSCC) , Feb. 2022.
16. T. He, Z. Kong, X. Liang, J. Luo, L. Lin, L. Qi, Y. Li, J. Zhao, G. Wang, "A 10-Mbps 119.2-pJ/bit Software Defined Body Channel Transceiver Employing a CCII-based PGA and a 2.5-bit/cycle ADC in 180-nm CMOS," 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2021, pp. 206-207, doi: 10.1109/ICTA53157.2021.9661912.
17. L. Fassio*, L. Lin*, R. De Rose, M. Lanuzza, F. Crupi and M. Alioto, "A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy," ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, pp. 343-346, doi: 10.1109/ESSCIRC53450.2021.9567778. (*equally credited authors)
18. Y. Dong, J. Li, L. Lin, T. Tang, J. H. Park, K. A. Ng, M. Zhang, L. Zhang, J. S. Y. Tan, J. Yoo., "Body-Coupled Power Transceiver with Node-Specific Body-Area Powering," ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, pp. 423-426, doi: 10.1109/ESSCIRC53450.2021.9567745.
19. L. Lin, K. A. Ahmed, P. S. Salamani and M. Alioto, "Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power Envelope," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2.
20. M. Zhang, L. Zhang, J. H. Park, C-W. Tsai, K. A. Ng, L. Lin, Y. Dong, J. Li, T. Tang, H. Wu, L. Wu, J. Yoo, "A One-Shot Learning, Online-Tuning, Closed-Loop Epilepsy Management SoC with 0.97μJ/Classification and 97.8% Vector-Based Sensitivity," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2, doi: 10.23919/VLSICircuits52068.2021.9492429.
21. L. Lin, S. Jain, M. Alioto, “Sub-nW Microcontroller with Dual-mode Standard Cells and Self-startup for Battery-Indifferent Sensor Nodes”, IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 5, pp. 1618-1629, May 2021, doi: 10.1109/JSSC.2020.3038115.
22. L. Fassio, F. Settino, L. Lin, R. De Rose, M. Lanuzza, F. Crupi, M. Alioto, "A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter," in IEEE Transactions on Circuits and Systems II: Express Briefs, early access, doi: 10.1109/TCSII.2020.3033253.
23. S. Jain, L. Lin, M. Alioto, "Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads," in IEEE Solid-State Circuits Letters, vol. 3, pp. 394-397, 2020, doi: 10.1109/LSSC.2020.3024838.
24. L. Lin, S. Jain, M. Alioto, “Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting”, 2020 Symposium on VLSI Circuit, Honolulu, HI, USA, 2020, pp. 1-2, doi: 10.1109/VLSICircuits18222.2020.9162898.
25. L. Fassio*, L. Lin*, R. Rose, M. Lanuzza, F. Crupi, M. Alioto, “A 0.25-V, 5.3-pW Voltage Reference with 25-μV/oC Temperature Coefficient, 140μV/V Line Sensitivity and 2,200-μm2 Area in 180nm”, 2020 Symposium on VLSI Circuit, Honolulu, HI, USA, 2020, pp. 1-2, doi: 10.1109/VLSICircuits18222.2020.9162872. (*equally credited authors)
26. S. Jain, L. Lin, M. Alioto, “Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling”, in IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 10, pp. 2670-2679, Oct. 2020, doi: 10.1109/JSSC.2020.3005778.
27. L. Lin, S. Jain, M. Alioto, “Integrated Power Management for Battery-Indifferent Systems with Ultra-Wide Adaptation down to nW”, in IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 4, pp. 967-976, April 2020, doi: 10.1109/JSSC.2019.2959742.
28. S. Jain, L. Lin, M. Alioto, “Automated Design of Reconfigurable Micro-Architectures for Accelerators under Wide Voltage Scaling”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 777-790, March 2020, doi: 10.1109/TVLSI.2019.2950959.
29. J. Li, Y. Dong, J. Park, L. Lin, T. Tang, M. Zhang, H. Wu, L. Zhang, J. S. Y. Tan, J. Yoo “Human-Body-Coupled Power-Delivery and Ambient-Energy-Harvesting ICs for a Full-Body-Area Power Sustainability”, 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 514-516, doi: 10.1109/ISSCC19947.2020.9063042.
30. S. Jain, L. Lin, M. Alioto, “Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling”, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, China, 2019, pp. 125-128, doi: 10.1109/A-SSCC47793.2019.9056919.
31. L. Lin, S. Jain, M. Alioto, "Reconfigurable Clock Networks for Wide Voltage Scaling," in IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 9, pp. 2622-2631, Sept. 2019, doi: 10.1109/JSSC.2019.2925269.
32. L. Lin, S. Jain, M. Alioto, “Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW”, 2019 Symposium on VLSI Circuit, Kyoto, Japan, 2019, pp. C178-C179, doi: 10.23919/VLSIC.2019.8778085.
33. O. Aiello, P. Crovetti, L. Lin, M. Alioto, “A pW-Power Hz-Range Oscillator Operating with a 0.3V-1.8V Unregulated Supply”, in IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 5, pp. 1487-1496, May 2019, doi: 10.1109/JSSC.2018.2886336.
34. L. Lin, S. Jain, M. Alioto, “A 595pW 14pJ/cycle Microcontroller with Dual-mode Standard Cells and Self-startup for Battery-Indifferent Distributed Sensing”, 2018 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, 2018, pp. 44-46, doi: 10.1109/ISSCC.2018.8310175.
35. S. Jain, L. Lin, M. Alioto, “Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures under Wide Voltage Scaling,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 53, no. 2, pp. 632-641, Feb. 2018, doi: 10.1109/JSSC.2017.2768406.
36. S. Jain, L. Lin, M. Alioto, “Design-Oriented Energy Models for Wide Voltage Scaling down to the Minimum Energy Point,” in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 64, no. 12, pp. 3115-3125, Dec. 2017, doi: 10.1109/TCSI.2017.2736540.
37. L. Lin, K. Trinh Quang, M. Alioto, “Transistor Sizing Strategy for Simultaneous Energy-Delay Optimization in CMOS Buffers”, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4, doi: 10.1109/ISCAS.2017.8050997.
38. L. Lin, S. Jain, M. Alioto, “Reconfigurable Clock Networks for Random Skew Mitigation from Sub-Threshold to Nominal Voltage”, 2017 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, 2017, pp. 440-441, doi: 10.1109/ISSCC.2017.7870450.